RISC-V Instruction Set is the seventh session of CPU 101.

Details of the Lecture

In this lecture, Engineer MIAO Yuyang will introduce RISC-V, one of the world’s most widely adopted open instruction set architectures. The lecture will provide practical guidance for those interested in designing their own CPUs.

Speaker Profile
MIAO Yuyang graduated with a Bachelor’s degree in Computer Science and Technology from Northwestern Polytechnical University. He currently works as an engineer in the Frontier Systems Laboratory at the Advanced Computer Systems Research Center of the Institute of Computing Technology, Chinese Academy of Sciences. He previously served as a teaching assistant for the “One Student One Chip” Initiative, participating in talent cultivation initiatives related to processor chips. Additionally, he has been involved in national major projects, responsible for tasks such as open-source PDK adaptation and open-source chip debugging.

Date & Time:
15:00 – 15:40 (Beijing Time, GMT+8)

September 4, 2026

Organizers

● Alliance of National and International Science Organizations for the Belt and Road Regions (ANSO)

● Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)

Online Access (Zoom Meeting)
Meeting ID: 878 1749 2402
Passcode: 885747

Meeting Link: 

https://us06web.zoom.us/j/87817492402?pwd=im2TO51bR4ElpZxDi4dhJj9QGcFubK.1